zur Hauptnavigation springen zum Inhaltsbereich springen

BayWISS-Kolleg Mobility and Transport www.baywiss.de

PhD-Projects in the Joint Academic Partnership Mobilität und Verkehr

Memory Profiling for Model Based Developed Software

On-chip cache allows fast data access and increases the program execution speed when executing from the cache. Caching the most recently accessed memory entries is the most common strategy implemented in the modern general-purpose processors. The founding observation behind is that the programs tend to reuse the data from the same memory region (i.e., spatial locality) over a short period of time (i.e., temporal locality). While this approach is likely to decrease the average execution time of the program, the worst-case can remain unaffected or even increase [?]. In the safety-critical airborne software, the worst-case execution time information has critical importance among the safety standard DO-178B objectives. The indeterministic bounds on the program execution time led in the past decades to the drastic measures in the software development practice such as disabling the processor cache. Fortunately, the static cache analysis for real-time systems has been recently an active research area and many cache-aware verification tools (e.g., AbsInt, Ottawa) have been developed. In this thesis, we address the next step in the full integration of the cache-based architecture in the software development cycle of the safety-critical systems. Typically, the complex airborne software systems are developed using model-based design tools (e.g., Simulink). Our first investigations showed that the code generation in these tools is cache-oblivious and can consequently lead to inefficient cache use. Especially, the look-up tables with the precalculated data that replace runtime computation may provoke cachethrashing during large data sets iterations. Our proposed solution for optimizing memory access includes program profiling through careful code instrumentation (e.g., Valgrind, PIP) and use of hardware cache management (e.g., cache lockdown, invalidation, prefetching, bypassing) for a predictable control of the cached content.



Supervisor Technical University of Munich:

Prof. Dr.-Ing. Florian Holzapfel


  • Flugsimulation und Flugdynamik
  • Flugregelung und Flugführung
  • Flugsteuerungsavionik und Flugsicherheit


Supervisor Technische Hochschule Ingolstadt:

Prof. em. Dr. Peter Hartlmüller

Ehemals Airbus Stiftungsprofessur „Systemtechnik in sicherheitsgerichteten Anwendungen“

an der Technische Hochschule Ingolstadt



  • Kommunikation in Echtzeitsystemen
  • Architektur eingebetteter Rechnersysteme
  • HW-nahe SW-Entwicklung


Micheal Saleab

Micheal Saleab

Technical University of Munich


Get in touch. We look forward to your questions and ideas for our Joint Academic Partnership Mobility and Transportation.

Judith Demharter

Judith Demharter

Technische Hochschule Ingolstadt
Esplanade 10
85049 Ingolstadt

Telephone: +49 841 93483789